1. Field of the Invention
The present disclosure is directed to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device including a multi-gate transistor.
2. Description of the Related Art
The size of a semiconductor device has become smaller due to high performance and high integration of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). As the semiconductor device becomes smaller, a gate length is reduced. It is difficult for a traditional planar single gate transistor to overcome performance degradation of the device due to the reduction of gate length. A multi-gate transistor has been studied as an alternative to the planar single-gate transistor.
The multi-gate transistor uses an upper surface and both sides as a channel, while the planar single-gate transistor uses one surface as a channel. Therefore, the multi-gate transistor can improve current by more than three times compared to the existing transistors.
In order to form a multi-gate transistor, active patterns having three-dimensional structure should be provided. An active pattern having a three-dimensional structure may be achieved by removing an isolation layer formed in the vicinity thereof. However, in the case where the active pattern are separated due to the misalignment of mask patterns when the isolation layer between the active patterns is removed, undesired channels may be formed in the separated active patterns. For this reason, the reliability of the device may be reduced, and the semiconductor device may have malfunctioned.